1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for forming a via plug for connecting a lower conductive layer and an upper conductive layer.
2. Description of Related Art
In the manufacture of a semiconductor device such as a DRAM, etching is generally performed under the condition that a lower-layer wiring is not removed even if overetching is done when forming a via hole by etching an interlayer insulating film on the lower-layer wiring (condition of a high selection ratio with respect to the lower-layer wiring), in a step of forming the via plug for connecting the lower-layer wiring and an upper-layer wiring, for example, in a step of forming the via plug in the structure after a lithography step shown in FIG. 6. In FIG. 6, reference numeral 21 denotes a semiconductor substrate, reference numeral 22 denotes a gate insulating film, reference numeral 23 denotes a gate electrode, reference numeral 24 denotes a silicon nitride film, reference numeral 25 denotes an interlayer insulating film, reference numeral 26 denotes a contact plug, reference numeral 27 denotes a lower-layer wiring, reference numeral 28 denotes an interlayer insulating film, and reference numeral 29 denotes a resist mask.
In addition, in the case of etching for forming a high-aspect-ratio via hole, etching needs to be performed under the condition of being able to secure resistance to a resist mask (condition of a high selection ratio with respect to the mask).
Under such a high selection ratio condition as described above, a deposition layer is easily formed within a hole, thus creating a condition in which etching is easily stopped by this deposition layer. If etching is performed under a high-ion energy condition in order to prevent this stop of etching, the deposition layer and a damage layer are formed in the bottom of the via hole.
Cross-section structures immediately after forming the via hole by performing etching under a high-selection ratio condition are shown in FIGS. 7A and 7B, wherein FIG. 7A shows a cross-section structure after a step following a step of forming the structure shown in FIG. 6 and FIG. 7B shows an enlarged cross-sectional view of an area near the circled portion of FIG. 7A (the contact plug 26 is omitted). As shown in FIG. 7B, a damage layer 31 and a deposition layer 32 are formed on the lower-layer wiring 27 in the bottom of a via hole 30. If the lower-layer wiring and the upper-layer wiring are connected by burying a conductive material in the hole and forming a via plug therein in the presence of such a damage layer and a deposition layer, the wirings do not conduct electricity or they go into a high-resistance state, thus significantly degrading the reliability of a finished semiconductor device.
Although the deposition layer is removed by a treatment of resist mask removal, the damage layer is not removed (FIGS. 8A and 8B). Accordingly, the damage layer is removed by means of light etching (FIGS. 9A and 9B). When this light etching is performed by means of dry etching, a gas containing oxygen and fluorine is used to remove the damage layer. In addition, the light etching is performed under a low-ion energy condition, in order to restrict the amount of abrasion in the lower-layer wiring as much as possible.
However, the amount of radicals and ions arriving at the bottom of the hole is small in the formation of a high-aspect-ratio via hole, thus leading to the insufficient removal of the damage layer. As a result, there probably occur a variation in contact resistance.
Japanese Patent Laid-Open No. 10-335450 (Patent Document 1) describes a method for suppressing contact resistance variations. This method will be described using FIGS. 10 to 12. In these figures, reference numeral 41 denotes a silicon substrate, reference numerals 42, 43 and 45 denote silicon dioxide films, reference numeral 44 denotes a lower-layer wiring (polysilicon layer), reference numeral 46 denotes a BPSG film, reference numeral 47 denotes a hole, reference numeral 48 denotes a barrier metal, reference numeral 49 denotes an electrical conductor, and reference numeral 50 denotes an upper-layer wiring.
In this method, the lower-layer wiring (polysilicon layer) 44 completely is etched within the hole, as shown in FIG. 11, with respect to the laminated structure shown in FIG. 10, when the hole 47 is formed in the formation of a plug for connecting the lower-layer wiring and the upper-layer wiring. Thus, the plug formed of the barrier metal 48 and the electrical conductor 49 is connected to the lower-layer wiring 44 at a side surface within the hole, as shown in FIG. 12. According to this method, an area of connection between the plug within the hole and the lower-layer wiring becomes smaller, when compared with a case in which etching for forming the hole is stopped at the upper portion of the lower-layer wiring 44. Thus, it is possible to reduce resistance variations, though contact resistance may increase. In addition, this method has a reduced number of steps as a method of hole formation Since the interlayer insulating film and the lower-layer wiring (polysilicon layer) are etched in the same step when forming the hole.
However, if the hole is formed by performing such etching as described above using a carbon (C)-containing resist mask, there is the possibility that C is introduced into the side surface of the lower-layer wiring during the etching. If C is present in the side surface within the hole where a contact is to be formed, there is the possibility of an altered layer being formed, thereby increasing contact resistance. The above-described problem does not occur if a contact hole is formed using a hard mask made of polysilicon or the like in place of the resist mask. As a result, however, the number of steps increases and so does the cost of manufacture.